1. Field of the Invention
The present invention relates to a semiconductor device and an information processing system including the same. More particularly, the present invention relates to a semiconductor device that includes plural core chips and an interface chip to control the cores and an information processing system including the same.
2. Description of the Related Art
A memory capacity that is required in a semiconductor device such as a dynamic random access memory (DRAM) has increased every year. In recent years, a memory device that is called a multi-chip package where plural memory chips are laminated is suggested to satisfy the required memory capacity. However, since the memory chip used in the multi-chip package is a common memory chip capable of operating even though the memory chip is a single chip, a so-called front end unit that performs a function of an interface with an external device (for example, memory controller) is included in each memory chip. For this reason, an area for a memory core in each memory chip is restricted to an area obtained by subtracting the area for the front end unit from a total chip area, and it is difficult to greatly increase a memory capacity for each chip (for each memory chip).
In addition, a circuit that constitutes the front end unit is manufactured at the same time as a back end unit including a memory core, regardless of the circuit being a circuit of a logic system. Therefore there have been a further problem that it is difficult to speed up the front end unit.
As a method to resolve the above problem, a method that integrates the front end unit and the back end unit in individual chips and laminates these chips, thereby constituting one semiconductor device, is suggested (for example, Japanese Patent Application Laid-Open (JP-A) No. 2007-157266). According to this method, with respect to plural core chips each of which is integrated with the back end unit without the front end unit, it becomes possible to increase a memory capacity for each chip (for each core chip) because an occupied area assignable for the memory core increases. Meanwhile, with respect to an interface chip that is integrated with the front end unit and is common to the plural core chips, it becomes possible to form its circuit with a high-speed transistor because the interface chip can be manufactured using a process different from that of the memory core. In addition, since the plural core chips can be allocated to one interface chip, it becomes possible to provide a semiconductor device that has a large memory capacity and a high operation speed as a whole.
JP-A No. 2007-157266 discloses a structure having DRAM chips stacked in five layers, having an interface chip stacked thereon, and having these chips connected to each other via a through silicon via (hereinafter, “TSV”). A stacked semiconductor device that exchanges internal data via the TSV needs to include a bidirectional buffer to drive the TSV having a large capacitance. Normally, a tri-state buffer capable of using an output in high impedance is used for this kind of bidirectional buffers (JP-A No. 2000-137644).
However, in a conventional chip-stacked semiconductor device having a bidirectional buffer connected to all TSVs of an interface chip and core chips, the logic level of the TSVs becomes unstable when output buffers in bidirectional buffers of all chips connected to one TSV are set at high impedance. As a result, a through current flows to an input buffer in the bidirectional buffers and the current consumption of the semiconductor device greatly increases.
Further, because any memory element is not mounted on the interface chip, the interface chip alone cannot test a read/write operation. Therefore, a defect of the interface chip is recognized after combining the interface chip with core chips. Accordingly, the entire semiconductor device including good core chips has to be discarded as a defective product. To solve this problem, there is a demand for a method of determining a defect of an interface chip at a wafer stage before stacking.